1. Field of the Invention
The present invention relates to the utilization of ceramic layers as patterning layers. More particularly, it relates to the use of ceramic layers to produce metal interconnect structures that are part of integrated circuits and microelectronic devices. Two primary advantages are provided by this invention. First, the processing of the ceramic layers is facile as films can be applied by any solvent based process, e.g., spin coating. Second, the unique chemical compositions of the ceramic layers provides substantial chemical contrast between typical layers that are applied by solution based processes.
2. Background Art
The utilization of hardmask patterning layers and buried etch stops is commonly used for the fabrication of metal interconnect structures, that are part of integrated circuits and microelectronic devices. A number of attributes are often required for the successful utilization of these layers. First, they should be definable by dry etching processes (e.g., reactive ion etch) with the use of lithographic masks and have compositions that provide chemical contrast to other layers so that structures can be easily generated. Second, they may be required to be resistant to photoresist rework steps, such as oxidizing plasmas, reducing plasmas, acidic wet baths, etc., that may be needed in cases where misalignment of patterning layers occur. Third, they must exhibit thermal stability so that they can withstand other processes that require elevated temperature processing. Fourth, they need sufficient adhesion to adjacent layers in order to withstand planarizing steps and other processes that produce stress on the interconnect structure. Depending on their placement and use, they may be required to either be removable with reasonable chemical mechanical polishing (CMP) rates or serve as a stop layer for chemical mechanical polishing. If these layers, are contained in the final interconnect structure, the dielectric constants must be low in order to minimize resistance-capacitance (RC) delays and enhance performance. Finally, they should be processable in a quick and cost effective manner.
Typically, hardmask patterning layers and buried etchstops are dielectrics systems that are deposited by chemical vapor deposition (CVD) and related methods. Although these processes allow the deposition of films having a variety of compositions including silicon oxides, silicon carbides, silicon nitrides, silicon carbonitrides, etc., they often involve costly manufacturing tools and can be process intensive and time consuming. In some cases, application of spin-on dielectrics have been proposed. However, these cases have been primarily limited to silsequioxanes, siloxanes, and other related chemistries that are primarily based on silicon-oxygen bonds.